H5TQ2G63BFR-H9C -2GB DDR3 RAM data bus

Features

-VDD=VDDQ=1.5V +/- 0.075V

-Fully differential clock inputs (CK, /CK) operation

-Differential Data Strobe (DQS, /DQS)

-On chip DLL align DQ, DQS and /DQS transition with CKtransition

-DM masks write data-in at the both rising and fallingedges of the data strobe

-All addresses and control inputs except data,data strobes and data masks latched on therising edges of the clock

-Programmable CAS latency 6, 7, 8, 9, 10 and (11) supported

-Programmable additive latency 0, CL-1, and CL-2supported

-Programmable CAS Write latency (CWL) = 5, 6, 7, 8

-Programmable burst length 4/8 with both nibblesequential and interleave mode

-BL switch on the fly

-8banks

-Average Refresh Cycle(Tcase of 0 °C~ 95 °C)
    - .8 µs at 0°C ~ 85 °C
    - 3.9 µs at 85°C ~ 95 °C

-Auto Self Refresh supported

-JEDEC standard 82ball FBGA(x4/x8), 96ball FBGA (x16)

-Driver strength selected by EMRS

-Dynamic On Die Termination supported

-Asynchronous RESET pin supported

-ZQ calibration supported

-TDQS (Termination Data Strobe) supported (x8 only)

-Write Levelization supported

-8 bit pre-fetch

-This product in compliance with the RoHS directive.